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Conference Papers Year : 2019

SIRM: Shift Insensitive Racetrack Main Memory

Hongbin Zhang
  • Function : Author
  • PersonId : 1161704
Bo Wei
  • Function : Author
  • PersonId : 1161705
Youyou Lu
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  • PersonId : 1161706
Jiwu Shu
  • Function : Author
  • PersonId : 1161707

Abstract

Racetrack memory (RM) is a potential DRAM alternative due to its high density and low energy cost and comparative access latency with SRAM. On this occasion, we propose a shift insensitive racetrack main memory architecture SIRM. SIRM provides uniform access latency to upper system, which make it easy to be managed. Experiments demonstrate that RM can outperform DRAM for main memory design with higher density and energy efficiency.
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hal-03770574 , version 1 (06-09-2022)

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Hongbin Zhang, Bo Wei, Youyou Lu, Jiwu Shu. SIRM: Shift Insensitive Racetrack Main Memory. 16th IFIP International Conference on Network and Parallel Computing (NPC), Aug 2019, Hohhot, China. pp.355-360, ⟨10.1007/978-3-030-30709-7_33⟩. ⟨hal-03770574⟩
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