An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing - VLSI-SoC: FromAlgorithms to Circuits and System-on-Chip Design Access content directly
Conference Papers Year : 2013

An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing

Abstract

Compressed sensing (CS) is a universal low-complexity data compression technique for signals that have a sparse representation in some domain. While CS data compression can be done both in the analog- and digital domain, digital implementations are often used on low-power sensor nodes, where an ultra-low-power (ULP) processor carries out the algorithm on Nyquist-rate sampled data. In such systems an energy-efficient implementation of the CS compression kernel is a vital ingredient to maximize battery lifetime. In this paper, we propose an application-specific instruction-set processor (ASIP) processor that has been optimized for CS data compression and for operation in the subthreshold (sub-VT) regime. The design is equipped with specific sub-VT capable standard-cell based memories, to enable low-voltage operation with low leakage. Our results show that the proposed ASIP accomplishes 62× speed-up and 11.6× power savings with respect to a straightforward CS implementation running on the baseline low-power processor without instruction set extensions.
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hal-01456963 , version 1 (06-02-2017)

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Jeremy Constantin, Ahmed Dogan, Oskar Andersson, Pascal Meinerzhagen, Joachim Rodrigues, et al.. An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing. 20th International Conference on Very Large Scale Integration (VLSI-SoC), Aug 2012, Santa Cruz, CA, United States. pp.88-106, ⟨10.1007/978-3-642-45073-0_5⟩. ⟨hal-01456963⟩
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