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Conference Papers Year : 1970

From Assertion-based Verification to Assertion-based Synthesis


We propose a linear complexity approach to achieve automatic synthesis of designs from temporal specifications. It uses concepts from the Assertion-Based Verification. Each property is turned into a component combining classical monitor and generator features: the extended-generator. We connect them with specific components to obtain a design that is correct by construction. It shortens the design flow by removing implementation and functional verification steps. Our approach synthesizes circuits specified by hundreds of temporal properties in a few seconds. Complex examples (i.e. conmax-ip and GenBuf) show the efficiency of the approach.
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hal-01478893 , version 1 (27-07-2017)


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Y. Oddos, Katell Morin-Allory, D. Borrione. From Assertion-based Verification to Assertion-based Synthesis. 17th International Conference on Very Large Scale Integration (VLSISOC), Oct 2009, Florianópolis, Brazil. pp.94-117, ⟨10.1007/978-3-642-23120-9_6⟩. ⟨hal-01478893⟩
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