SIRM: Shift Insensitive Racetrack Main Memory
Abstract
Racetrack memory (RM) is a potential DRAM alternative due to its high density and low energy cost and comparative access latency with SRAM. On this occasion, we propose a shift insensitive racetrack main memory architecture SIRM. SIRM provides uniform access latency to upper system, which make it easy to be managed. Experiments demonstrate that RM can outperform DRAM for main memory design with higher density and energy efficiency.
Domains
Computer Science [cs]| Origin | Files produced by the author(s) |
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