The scaling of common architectures for data-intensive applications is limited by the memory wall issues that culminate in energy and performance losses. Near-data or Processing in Memory (PIM) approach has been revisited to tackle this problem, along with a wide variety of architectural designs. However, these devices commonly rely on Application Specific Integrated Circuit (ASIC) designs, which in turn fail to cover the heterogeneity found in such applications. This paper discusses and exploits the heterogeneity present in the data-intensive realm by using a range of permutations for the tuple (algorithm, dataset, programming language). Relying on commonplace hardware performance metrics, we show how to identify the main changes in the processing demands and select the best near-data configuration. Using the proposed strategy, one could see a performance difference of 1.52x, and an Energy Delay Product of 2.86x in the studied examples.