SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays - VLSI-SoC: Design Trends Access content directly
Conference Papers Year : 2021

SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays

Abstract

Recently, it has been common to use parallel processing for machine learning. CGRAs are drawing attention in terms of reconfigurability and high performance. We propose a method to map data-flow graphs onto CGRAs by SAT solving. The proposed method can perform the automatic transformation which changes the order of operations in data-flow graphs to obtain more efficient schedules. It also accommodates mapping of multi-node operations like MAC operation. We have solved mapping problems of matrix-vector multiplication. In our experiment, a SAT solver outperformed an ILP solver. Our method successfully processed a data-flow graph of more than a hundred nodes. The automatic transformation under the associative and commutative laws was not as much scalable but successfully reduced the number of cycles, where the XBTree-based method worked faster than the enumeration-based method. As another direction, we tried to optimize a CGRA architecture according to a data-flow graph and were able to reduce its PEs and connections through incremental SAT solving.
Fichier principal
Vignette du fichier
512096_1_En_6_Chapter.pdf (779.79 Ko) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

hal-03759734 , version 1 (24-08-2022)

Licence

Attribution

Identifiers

Cite

Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek. SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays. 28th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2020, Salt Lake City, UT, United States. pp.113-131, ⟨10.1007/978-3-030-81641-4_6⟩. ⟨hal-03759734⟩
53 View
9 Download

Altmetric

Share

Gmail Facebook X LinkedIn More