RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique - VLSI-SoC: Design Trends Access content directly
Conference Papers Year : 2021

RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique

Jonas Gava
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Ricardo Reis
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Abstract

To achieve a substantial reliability and safety level, it is imperative to provide electronic computing systems with appropriate mechanisms to tackle soft errors. This paper proposes a low-cost system-level soft error mitigation technique, which allocates the critical application function to a pool of specific general-purpose processor registers. Both the critical function and the register pool are automatically selected by a developed profiling tool. The proposed technique was validated through more than 400K fault injections considering a Linux kernel, different benchmarks, and two multicore Arm processor architectures (ARMv7-A and ARMv8-A). Results show that our technique significantly reduces the code size and performance overheads while providing soft error reliability improvement compared with the Triple Modular Redundancy (TMR) technique.
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hal-03759727 , version 1 (24-08-2022)

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Jonas Gava, Ricardo Reis, Luciano Ost. RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique. 28th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2020, Salt Lake City, UT, United States. pp.235-253, ⟨10.1007/978-3-030-81641-4_11⟩. ⟨hal-03759727⟩
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