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Conference Papers Year : 2021

Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector

Abstract

A hybrid analog/digital signal processor has been proposed to implement energy-efficient multi-input-multi-output (MIMO) detectors. A sub-optimum MIMO detector based on Markov Chain Monte Carlo (MCMC) algorithm for a 4 $$\times $$× 4 MIMO system is presented. A careful partitioning between analog and digital domains has been made to reduce system power consumption. The outputs of the proposed analog signal processing unit are being converted to digital using a low-resolution analog-to-digital converter (ADC), to deliver the signals to the digital portion of the detector system. The proposed 4 $$\times $$× 4 MCMC MIMO detector is designed in a standard 45 nm CMOS technology, that consumes 29.3 mW from 1.0 V supply. A throughput of 235.3 Mbps is achieved, while operating at 1.0 GHz clock frequency. The design occupies a 0.11 mm$$^2$$2 silicon area.
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hal-03759723 , version 1 (24-08-2022)

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Amin Aghighi, Behrouz Farhang-Boroujeny, Armin Tajalli. Mixed-Mode Signal Processing for Implementing MCMC MIMO Detector. 28th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2020, Salt Lake City, UT, United States. pp.21-37, ⟨10.1007/978-3-030-81641-4_2⟩. ⟨hal-03759723⟩
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