index - VLSI-SoC: New Technology Enabler 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019 Cusco, Peru, October 6–9, 2019 Revised and Extended Selected Papers
   


Full Text Documents

15

Search


Table of Contents
VLSI-SoC: New Technology Enabler
Carolina Metzler, Pierre-Emmanuel Gaillardon, Giovanni de Micheli, Carlos Silva-Cardenas, Ricardo Reis
Front Matter
Software-Based Self-Test for Delay Faults
Michelangelo Grosso, Matteo Sonza Reorda, Salvatore Rinaudo
1-19
On Test Generation for Microprocessors for Extended Class of Functional Faults
Adeboye Oyeniran, Raimund Ubar, Maksim Jenihhin, Jaan Raik
21-44
Robust FinFET Schmitt Trigger Designs for Low Power Applications
Leonardo Moraes, Alexandra Zimpeck, Cristina Meinhardt, Ricardo Reis
45-68
An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults
Rafael Schvittz, Denis Franco, Leomar da Rosa, Paulo Butzen
69-88
Process Variability Impact on the SET Response of FinFET Multi-level Design
Leonardo Brendler, Alexandra Zimpeck, Cristina Meinhardt, Ricardo Reis
89-113
Efficient Soft Error Vulnerability Analysis Using Non-intrusive Fault Injection Techniques
Vitor Bandeira, Felipe Rosa, Ricardo Reis, Luciano Ost
115-137
A Statistical Wafer Scale Error and Redundancy Analysis Simulator
Atishay Atishay, Ankit Gupta, Rashmi Sonawat, Helik Thacker, B. Prasanth
139-163
Hardware-Enabled Secure Firmware Updates in Embedded Systems
Solon Falas, Charalambos Konstantinou, Maria Michael
165-185
Reliability Enhanced Digital Low-Dropout Regulator with Improved Transient Performance
Longfei Wang, Soner Seçkiner, Selçuk Köse
187-208
Security Aspects of Real-Time MPSoCs: The Flaws and Opportunities of Preemptive NoCs
Bruno Forlin, Cezar Reinbrecht, Johanna Sepúlveda
209-233
Offset-Compensation Systems for Multi-Gbit/s Optical Receivers
László Szilágyi, Jan Pliva, Ronny Henker
235-255
Accelerating Inference on Binary Neural Networks with Digital RRAM Processing
David Atienza, Pierre-Emmanuel Gaillardon, João Vieira, Edouard Giacomin, Yasir Qureshi, Marina Zapater, Xifan Tang, Shahar Kvatinsky
257-278
Semi- and Fully-Random Access LUTs for Smooth Functions
Y. Gener, Furkan Aydin, Sezer Gören, H. Ugurdag
279-306
A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors
Patsy Cadareanu, Ganesh Gore, Edouard Giacomin, Pierre-Emmanuel Gaillardon
307-322
Exploiting Heterogeneous Mobile Architectures Through a Unified Runtime Framework
Chenying Hsieh, Ardalan Sani, Nikil Dutt
323-344

 


Designed by Inria-IES Team : http://hal.inria.fr/    Hosted by HAL : http://hal.archives-ouvertes.fr/