Rapid, High-Level Performance Estimation for DSE Using Calibrated Weight Tables - System Level Design from HW/SW to Memory for Embedded Systems
Conference Papers Year : 2017

Rapid, High-Level Performance Estimation for DSE Using Calibrated Weight Tables

Kasra Moazzemi
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  • PersonId : 1035328
Smit Patel
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  • PersonId : 1035333
Gunar Schirner
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  • PersonId : 1001408

Abstract

Automated Design Space Exploration (DSE) is a critical part of system-level design. It relies on performance estimation to evaluate design alternatives. However, since a plethora of design alternatives need to be compared, the run-time of performance estimation itself may pose a bottleneck. In DSE, fastest performance estimation is of essence while some accuracy may be sacrificed. Fast estimation can be realised through capturing application demand, as well as Processing Element (PE) supply (later on called weight table) in a matrix each. Then, performance estimation (retargeting) is reduced to a matrix multiplication. However, defining the weight table from a data sheet is impractical due to the multitude of (micro-) architecture aspects.This paper introduces a novel methodology, WeiCal, for automatically generating Weight Tables in the context of C source-level estimation using application profiling and Linear Programming (LP). LP solving is based on the measured performance of training benchmarks on an actual PE. We validated WeiCal using a synthetic processor and benchmark model, and also analyse the impact of non-observable features on estimation accuracy. We evaluate the efficiency using 49 benchmarks on 2 different processors with varying configurations (multiple memory configurations and software optimizations). On a 3.1 GHz i5-3450 Intel host, 25 million estimations/second can be obtained regardless of the application size and PE complexity. The accuracy is sufficient for early DSE with a 24% average error.
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hal-01854171 , version 1 (06-08-2018)

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Kasra Moazzemi, Smit Patel, Shen Feng, Gunar Schirner. Rapid, High-Level Performance Estimation for DSE Using Calibrated Weight Tables. 5th International Embedded Systems Symposium (IESS), Nov 2015, Foz do Iguaçu, Brazil. pp.197-209, ⟨10.1007/978-3-319-90023-0_16⟩. ⟨hal-01854171⟩
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