Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs - System Level Design from HW/SW to Memory for Embedded Systems Access content directly
Conference Papers Year : 2017

Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs

Abstract

Current approaches for mapping Kahn Process Networks (KPN) and Dynamic Data Flow (DDF) applications rely on assumptions on the program behavior specific to an execution. Thus, a near-optimal mapping, computed for a given input data set, may become sub-optimal at run-time. This happens when a different data set induces a significantly different behavior. We address this problem by leveraging inherent mathematical structures of the dataflow models and the hardware architectures. On the side of the dataflow models, we rely on the monoid structure of histories and traces. This structure help us formalize the behavior of multiple executions of a given dynamic application. By defining metrics we have a formal framework for comparing the executions. On the side of the hardware, we take advantage of symmetries in the architecture to reduce the search space for the mapping problem. We evaluate our implementation on execution variations of a randomly-generated KPN application and on a low-variation JPEG encoder benchmark. Using the described methods we show that trace differences are not sufficient for characterizing performance losses. Additionally, using platform symmetries we manage to reduce the design space in the experiments by two orders of magnitude.
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hal-01854169 , version 1 (06-08-2018)

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Andrés Goens, Jeronimo Castrillon. Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs. 5th International Embedded Systems Symposium (IESS), Nov 2015, Foz do Iguaçu, Brazil. pp.116-127, ⟨10.1007/978-3-319-90023-0_10⟩. ⟨hal-01854169⟩
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