Parallel Algorithm of SOI Layout Decomposition for Double Patterning Lithography on High-Performance Computer Platforms - Technological Innovation for Collective Awareness Systems (DoCEIS 2014) Access content directly
Conference Papers Year : 2014

Parallel Algorithm of SOI Layout Decomposition for Double Patterning Lithography on High-Performance Computer Platforms

Vladimir Verstov
  • Function : Author
  • PersonId : 976824
Vadim Shakhnov
  • Function : Author
  • PersonId : 976825
Lyudmila Zinchenko
  • Function : Author
  • PersonId : 976826

Abstract

In the paper silicon on insulator layout decomposition algorithms for the double patterning lithography on high performance computing platforms are discussed. Our approach is based on the use of a contradiction graph and a modified concurrent breadth-first search algorithm. We evaluate our technique on both real-world and artificial test cases including non-Manhattan geometry. Experimental results show that our soft computing algorithms decompose layout successfully and a minimal distance between polygons in layout is increased.
Fichier principal
Vignette du fichier
978-3-642-54734-8_60_Chapter.pdf (4 Ko) Télécharger le fichier
Origin : Files produced by the author(s)
Loading...

Dates and versions

hal-01274821 , version 1 (16-02-2016)

Licence

Attribution

Identifiers

Cite

Vladimir Verstov, Vadim Shakhnov, Lyudmila Zinchenko. Parallel Algorithm of SOI Layout Decomposition for Double Patterning Lithography on High-Performance Computer Platforms. 5th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS), Apr 2014, Costa de Caparica, Portugal. pp.543-550, ⟨10.1007/978-3-642-54734-8_60⟩. ⟨hal-01274821⟩
58 View
137 Download

Altmetric

Share

Gmail Facebook X LinkedIn More