Multiplierless Design of Linear DSP Transforms - VLSI-SoC: Advanced Research for Systems on Chip Access content directly
Conference Papers Year : 2012

Multiplierless Design of Linear DSP Transforms


The last two decades have seen tremendous effort on the development of high-level algorithms for the multiplierless design of constant multiplications, i.e., using only addition, subtraction, and shift operations. Among the different types of constant multiplications, the multiplication of a constant matrix by an input vector, i.e., the constant matrix-vector multiplication (CMVM) operation, is the most general case and occurs in many digital signal processing (DSP) systems. This chapter addresses the problem of minimizing the number of addition and subtraction operations in a CMVM operation and introduces a hybrid algorithm that incorporates efficient techniques. This chapter also describes how the hybrid algorithm can be modified to handle a delay constraint. The experimental results on a comprehensive set of instances show the efficiency of the hybrid algorithms at both high-level and gate-level, in comparison to previously proposed methods.
Fichier principal
Vignette du fichier
978-3-642-32770-4_5_Chapter.pdf (194.85 Ko) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

hal-01519768 , version 1 (09-05-2017)





Levent Aksoy, Eduardo Da Costa, Paulo Flores, José Monteiro. Multiplierless Design of Linear DSP Transforms. 19th International Conference on Very Large Scale Integration (VLSISOC), Oct 2011, Hong Kong, China. pp.73-93, ⟨10.1007/978-3-642-32770-4_5⟩. ⟨hal-01519768⟩
143 View
87 Download



Gmail Facebook X LinkedIn More